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graphene quilts for thermal management of high-power gan transistors

by:Mingfa Tech     2020-01-24
Heating is a serious problem for people with high heat.
Power gan (GaN)
Electronic and optoelectronic devices.
Various thermal management solutions, for example
Chip connections or composite substrates have been tried.
However, temperature rise due to heat dissipation still limits the application of nitrogen
Based on technology.
Here we show that the thermal management of GaN transistors can be significantly improved by introducing alternative heat
Escape passage with little realizationlayer graphene—
An excellent thermal conductor.
A graphene-graphite layer is formed on the AlGaN/GaN transistor on the SiC substrate. Using micro-
Raman spectrum for on-site monitoring we demonstrate that the temperature of hot spots can be reduced by 20 °c in transistors operating at 13 W MM-1, which is equivalent to an orderof-
Increase in equipment life.
The simulation shows that the graphene layer performs better in GaN devices on sapphire substrate.
The local thermal diffusion of the materials proposed to maintain their thermal properties on the nano-scale represents a transformative change in thermal management.
FLG films need to be transferred on the AlGaN/GaN device to place them precisely at the drain electrode position.
The channel area between the gate and the drain generates most of the heat.
FLG films should not be exposed to other exposed electrodes and should be attached to larger graphite rods that act as radiators.
We have adopted a method that uses jumeijin as a supporting film to transfer it to the desired location, but modified it for our purposes ().
The innovation of the transfer procedure we introduced was that we coated the substrate with poly-cost, and then stripped the graphene on the substrate.
Therefore, only one side of the FLG is exposed to another material that reduces the possible residue.
First of all, we spin a layer of anti-photoresist (Shipley 1813)with 3,500 r. p. m.
And bake 90 seconds at 110 °c.
The substrate is then irradiated with ultraviolet light.
The second layer polymer pmma5 was applied with 3,500 r spin. p. m.
Bake for 90 seconds at 130 °c
We then mechanically peel off from HOPG to produce graphene on the substrate.
After the coating procedure is completed, the FLG film (Even singlelayer graphene)
Optical identification can be performed under a microscope.
After completing the procedure, we immersed the sample in photoresist developer (AZ400/HO=1:4)
Dissolved photo-resistance.
What floats in the liquid is the silicone film.
We use metal slides with holes to connect the Poly gold film.
Note that the location of the FLG films is roughly estimated to make sure they fall into the hole.
After removing the film from the liquid, the metal slide is mounted on a micro-manipulator for calibration.
We were able to see the FLG film through holes under an optical microscope and adjust the position of the substrate to place graphene at the top of the desired position.
The silicone film is dissolved by hot acetone, so that the FLG film is attached to the substrate. A finite-
The elemental method has been used to investigate the thermal diffusion in the structure of the AlGaN/GaN HFET studied in the case of a graphene heat sink and a graphene-free heat sink.
Shown as a schematic diagram of the structure of the simulator.
The overall size of the simulation domain is 600 μm, which is much larger than the characteristic size of the device.
The thickness of SiC, GaN, AlGaN and SiO layers is 400 μm, 500 nm, 30 nm and 10 nm, respectively.
It is concluded from the literature that their corresponding thermal conductivity is = 350, 160, 120 and 1, respectively.
4 w mK respectively.
The thermal resistance of the resulting structure with the assumed value is consistent with the measurement of the effective thermal conductivity of the device structure.
The gate thickness is 120 nm and the drain and source thickness is 240 nm.
Considering that the main component of the electrode is gold, we used = 320 W mK under RT.
The heat source is rectangular, 4-μ m width and 10-nm thickness.
It is placed on the interface of the drain and GaN layers, at the drain-
Door opening near one side of the gate.
TBR influence on GaN substrate interface
Heating effect in GaN transistor.
TBR is modeled between the GaN Channel and the SiC substrate with a virtual thermal isolation layer of small thickness.
The effective thermal conductivity of the layer is defined as, where TBR at the GaN-SiC interface. We adopted =1.
5x10 mK W from the reported experimental study.
Heat diffusion is simulated by numerical solving the Fourier equation with appropriate boundary conditions.
The bottom of the SiC substrate and the left side of the graphene radiator maintain a constant temperature = 25 °c.
The external surface is modeled as insulated from the environment.
The triangular mesh is generated by the structure studied for numerical solution ().
After verifying this model with experimental data, we simulated the temperature distribution in the AlGaN/GaN hfet with and without graphene-graphite heat sink.
In the uncertainty range of 10%, the simulation results are consistent with the experimental data.
In order to estimate the optimal conditions that can be achieved by graphene-graphite quilts, we conducted several simulations with different radiator designs.
In most simulation operations, we assume that the FLG film consists of ten layers of carbon atoms.
The position of the top surface radiator is at the selected distance within the range of 1 to 50 μm.
The correlation between Delta and radiator distance is shown in.
The device structure close to the radiator provides a stronger Delta reduction.
At = 1 μm, the maximum Δ32 °c reduction can be obtained for a given power density and device structure.
In the actual design, the nearby radiator is attached to the top
Vertical heat channels can be used to achieve surface heat dissipation.
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